DesignCon 2014 Distributed Modeling and Characterization of On - Chip / System Level PDN and Jitter Impact

The constant pursuit of higher operating speeds combined with the effort to reduce power consumption creates increasingly stringent requirements for modern I/O interfaces. As the voltage margins shrink and the operating frequencies increase, the quality of the power delivery network becomes the critical factor that determines the I/O performance. A successful I/O design depends on having a robust and reliable power supply at all levels of the system. This paper describes a methodology flow that enables characterization of a system-level power delivery network. The methodology takes into consideration the combined effects of chip, package, and board-level components of a power supply. The system approach results in a very accurate prediction of the power supply noise and of its impact on the system timing. The characterization flow brings together different commercial computer-aided engineering tools as well as some in-house techniques to create a complete model of a power delivery network. The correlation and verification steps use several types of Xilinx FPGA products as test vehicles, and leverage the flexibility offered by FPGAs to measure the parameters of the system. Modeling and measurements are done both in frequency and time domains. Such characteristics of the system as frequency-dependent power delivery network impedance, transient voltage noise, I/O phase noise, and jitter are all considered.